1. Field of the Invention
The present invention relates to data transmission and detection systems and more particularly to a system which transmits serial data of bits and a system which detects the serial data.
2. Related Background Art
In recently proposed video floppy systems, it is proposed to record a video signal as well as an audio signal on a magnetic sheet as the recording medium.
FIG. 1 diagrammatically shows both the video and audio signals present together on a magnetic sheet. For example, according to the standards on video floppies, field video signals (V) and audio signals (A1, A2) all can be recorded on a magnetic sheet for up to 50 concentric tracks in all. The audio signal is raised by time base compression into the video band and recorded in a frequency modulated form. The recording time per track is approximately 10 seconds, assuming that the audio band is 5 KHz and the time base compression ratio is 640. Also, assuming that the audio band is 2.5 MHz and the time base compression ratio is 1,280, recording for approximately 20 seconds is possible. In this case, the audio signal may be completed in a single track or extended into the next track.
The ring-like audio track is divided into four sectors, as shown in FIG. 2. For example, in the mode where recording for 10 seconds is possible, an amount of information for 2.5 seconds is allotted to each sector.
FIG. 3 illustrates the form of an audio signal and additional signals to be recorded on a single sector.
In FIG. 3, after an elapse of tl from time T.sub.0, a start ID signal having a level L.sub.H higher than a reference level L.sub.0 continues for time t.sub.2 for obtaining the timing to read the audio signal information. After a blank of t.sub.3, the audio signal starts. During the first interval of time t.sub.4 the signal on a sector overlaps with that on the just preceding sector. This does not occur in the first sector corresponding to the leading portion of the audio signal. A new audio signal is for the remaining time t.sub.5, the length of which is variable; 2.5 seconds at a maximum in the mode of 10 seconds per track, as mentioned above. After a subsequent blank of t.sub.6, an end ID signal having a level of L.sub.L lower than reference level L.sub.0 continues for t.sub.7 in order to permit detection of the end of the audio signal and to obtain the timing of reading data signal related to the subsequent audio signal. After a blank of t.sub.8, the data interval continues for t.sub.9. Then a blanking interval of time t.sub.10 appears, the length of which is varied according to the interval of the preceding audio signal t.sub.5, and thus one sector cycle ends. This form is basically the same in any of the sectors where the audio signal is present. The interval of the audio signal shown by t.sub.5 is variable and selected so that the interval t.sub.5 +t.sub.10 is constant at all times. Thus the length of the audio signal determines the position of the end ID and data signals.
The data signal includes, in the form of digital data, the number, on the magnetic sheet, of a track on which the audio signal is recorded, the number of the leading and subsequent tracks through which audio signals are recorded continuously, the number of the tracks through which the video signal corresponding to the audio signal is recorded, the compression ratio of the audio signal, etc. In this case, it is arranged that "1" and "0" represent levels L.sub.0 and L.sub.L, respectively.
When subjected to frequency modulation, the voltage levels L.sub.0, L.sub.H, and L.sub.L correspond to f.sub.0, f.sub.H and f.sub.L modulation frequencies, respectively, where f.sub.L &lt;f.sub.0 &lt;f.sub.H ; for example, f.sub.0 =6 MHz, f.sub.H =7 MHz, f.sub.L =5 MHz.
The above data signal will now be described in more detail.
FIG. 4 illustrates on an enlarged scale the data signal shown in FIG. 3.
In FIG. 4, reference numeral 51 denotes synchronism bits of 1 byte. Reference numerals 52-59 denote data signals of 1 byte each; all of the data signals 52-59 thus include 8 bytes in all. Of the 8-byte data for the signals 52-59, for example, 6 bytes for the signals 52-57 are used as the net data bits and 2 bytes for the remaining signals 58 and 59 are used as the CRCC (cyclic redundancy check code) for error detection. Here, the 8 bytes for the signals 52-59, inclusive of CRCC, will be described hereinafter as the "data". Thus the data signal of FIG. 4 is composed of the 1 byte of synchronism bits and the 8 byte of data bits. The type of the codes used is an NRZ code where low and high levels are represented by "0" and "1", respectively. The total number of bits used is 72. As described above, the net 6-byte data includes the track number of the audio signal tracks, the time compression ratio of the audio signal, the track number of the corresponding video, the track number of the leading and trailing tracks through which the audio signal continues, etc.
FIG. 5 shows one example of a circuit to produce the data signal of FIG. 4.
In FIG. 5, a signal generator 60 generates a start, and an end ID signals and a clock signal to read a 9-byte, (=72-bit) data shift register 63. An adder 61 adds a start ID signal and an end ID signal from signal generator 60 to a data signal from shift register 63. A selector 62 selects which of the bytes of shift register 63 should be connected to the output of a controller 12 including a microcomputer.
The operation of the FIG. 5 circuit concerning data generation will now be described. First, controller 12 controls selector 62 so that the one-byte synchronism signal and predetermined data are written into a byte area 0 (the least significant byte area) and more significant byte areas 1-8, respectively, of shift register 63 in bytes in parallel form sequentially from byte area 0 to byte area 8 (the most significant byte area). In this case, the synchronism signal of 1 byte written into the least significant byte area 0 is represented, for example, by "01010101". As described above, the net data is written into byte areas 1-6 and the CRCC into byte areas 7 and 8. When this writing has been completed, controller 12, for example, enables signal generator 60 to generate a read clock signal (a) at a predetermined timing synchronous with rotation of the magnetic sheet (the timing is, for example, determined on the basis of PG signals, etc., derived by detection of rotating phase indicia attached to part of the magnetic sheet). The clock signal (a) causes the contents of shift register 63 to be read in bit serial form sequentially from byte 0 to byte 8 and a signal train having the form of FIG. 4 is obtained at the output (b) of the register 63. This output (b) of the register is added by adder 61 to the start and end ID signals (c) from signal generator 60.
The output (d) of adder 61 is then synthesized with a compressed audio signal into a signal having the format shown in FIG. 3. The adder output is then subjected to processing including emphasis, frequency modulation, etc., and recorded on the magnetic sheet via a magnetic head. In this case, if the recording speed is 1 TV field/track, the magnetic sheet will be rotated at 3,600 rpm under the NTSC system and concentric recording tracks will be formed.
The leading bit output of shift register 63 is connected to the trailing end bit input thereof, which is not shown here. Thus in order to record data for one sector, data is circulated and written into the shift register 63 even after the data has been read out once, and when the second and subsequent sectors are to be recorded, the data will be read and recorded again and again.
Reproduction of the signal recorded in the above mentioned manner will now be described. Here, especially, reproduction of the data will be described and reproduction of the compressed audio signal, etc., will be omitted.
FIG. 6 illustrates an example of a circuit to reproduce the data. In FIG. 6, reference numeral 10 denotes a magnetic sheet. A sheet rotating motor 11 is controlled so as to rotate at 3,600 rpm in accordance with the NTSC system in view of a recording speed of 1 TV field/track. A PG detector 13 detects the rotating indicia on the sheet 10 and produces a PG signal. The circuit of FIG. 6 further includes a magnetic head 14, a reproduction preamplifier 22, a frequency demodulator 26, a deemphasis circuit 27, a voice reproduce circuit 28, an ID separator 29 which separates the start and end ID signals, a data gate pulse generator 30, a data gate 31, a data synchronism detector 32, a signal generator 33, a 8-byte data store shift register 64, and a selector 65. Shift register 64 may also be used as shift register 63 of FIG. 5.
In the above structure, the FM signal picked up by magnetic head 14 out of magnetic sheet 10 is amplified by preamplifier 22 to a predetermined level and then delivered to frequency demodulator 26. The signal demodulated by demodulator 26 is deemphasized by deemphasis circuit 27 into a signal having the format shown in FIG. 3. This signal is delivered to voice reproduce circuit 28 where the audio portion of the signal is subjected to predetermined processing and then expanded into the original signal. Thus the original audio signal is reproduced.
The reproduced signal from deemphasis circuit 27 is also delivered to ID separator 29 and data gate 31. The ID separator 29 is basically a low-pass filter, the cut-off frequency of which is set so that the ID signal can pass through the filter and that no audio and data signals can pass. The start and end ID signals (e) separated by ID separator 29 are delivered to data gate pulse generator circuit 30 which separates only the end ID signals on the basis of the PG signal output from PG detector 13 which detects the rotating indicia on the magnetic sheet 10. The data gate pulse generator 30 produces a data gate pulse (f) to extract only the data portion on the basis of one of the four end ID signals for the four sectors designated by controller 12. The data gate pulse (f) is delivered to data gate 31, which separates only the data signal (g), inclusive of the synchronism portion, from the reproduced signal having substantially the format of FIG. 3. The separated data signal (g) is then delivered to shift register 64 and data synchronism detector 32. Synchronism detector 32 detects the synchronism bits at the head of the incoming data signal such as is shown in FIG. 4 and is composed of a shift register, a counter, a logic gate, etc. This will be described in more detail hereinafter. The clock signal (h) which is input by signal generator 33 is, for example, 3 f.sub.sc, assuming that the bit rate is f.sub.sc /2 bits/sec (PBS), where f.sub.sc =3.579545 MHz which is the color subcarrier frequency in the NTSC system. The counter which divides the clock signal (h) by a factor of, for example, of 6 is reset by the first rise of the synchronism bits. Each of the pulses of the 6-divided clock signal is adjusted to coincide with the central position of a respective one of the synchronism bits and the thus obtained clock pulses are applied as the write clock pulses to the 8-bit shift register to write the synchronism bits thereinto. The 8 outputs of the shift register are coupled to the logic gate which outputs, for example, "1" when the register output takes the pattern "01010101". Thus when the synchronism detector 32 detects the synchronism bits of data, it outputs a detection pulse (i) which is applied to signal generator 33. This resets another divide by 6 frequency circuit in the signal generator 33 which counts down the 3 f.sub.sc. Thus signal generator 33 produces write clock signal (j), reset in timing, the pulses of which are applied sequentially to shift register 64. In response to these pulses the shift register writes thereon in a bit serial manner the bit data of, for example, of 8 bytes of the data signal 52-59 of FIG. 4 excluding the synchronism bits of the data signal. When signal generator 33 has generated write clock pulses for 8 bytes, it delivers a write end pulse (k) to controller 12. In response to the write end pulse the controller 12 starts to read the data from shift register 64. That is, controller 12 controls selector 65 such that same selects a respective one of the bytes of shift register 64 sequentially from the least significant byte (byte 0) to the most significant byte (7) and reads the corresponding data in a bit parallel manner. When this reading has been completed, controller 12 again controls data gate pulse generator 30 so that same produces a data gate pulse (f) corresponding to the end ID signal in another sector. This causes reading operation similar to the above to be repeated. This reading operation will end when it has been repeated for four sectors, i.e. four times.
The data transmission (recording) and detection (reproduction) system which forms the background techniques of the present invention and which has just been described, has the following problems.
Assume, that the bit rate for data recording is f.sub.sc /2 BPS, i.e., 1.7897725 MBPS and that the rotating speed of the magnetic sheet is ideally 3,600 rpm both in recording and in reproduction. Then the read clock frequency for reproduction may be 1.7897725 MHz. However, the rotation of the, magnetic sheet may contain jitter due to nonuniform motor rotation. The center of the concentric recording tracks may be deviated from the center of rotation of the sheet due to changes in the accuracy of the sheet being plased on the motor spindle, for example, in recording and reproduction. In such a case, the resulting reproduced signal would contain jitter.
According to the inventors' experiment, the quantity of this jitter was no less than .+-.2% at its worst and data which had been recorded at a bit rate of 1.7897725 MBPS was reproduced at a bit rate fluctuating between 1.754 and 1.826 MBPS. In this case, the fluctuating period is 16.7 m sec corresponding to the magnetic sheet rotation speed at 3,600 rpm (60 Hz). On the other hand, the interval of each data bit is about 36 .mu.sec (for 8 bytes, the bit rate is as short as 1.7897725 MBPS). Thus if data is written when the bit rate has fluctuated to 1.754 MBPS, the write clock frequency at that time should be essentially 1.754 MHz. In this case, however, data signal is only present discretely at 90-degree intervals with a width of about 36 .mu.sec on a single track, the period of which is 16.7 m sec. The type of codes used is an NRZ which itself has no clock pulse components. Therefore, it is difficult to cause the write clock signal to follow the frequency at 1.754 MHz using means such as a PLL and thus there is no method other than detection of the data, e.g., or writing of same into the shift register, using a fixed-frequency clock signal of 1.7897725 MHz which is the same as that used in recording.
FIG. 7 illustrates an example where the data having a bit rate of 1.754 MBPS is detected or written into the shift register using a write clock frequency of 1.7897725 MHz. As shown in FIG. 7, if the write clock frequency and the data bit rate are deviated 2% from each other, a read error will occur midway in the byte 3 (at the fourth byte) indicated by X in FIG. 7.
As described above, in the data recording and reproduction system described with respect to FIGS. 4-6, although the write clock is reset and synchronized by the first synchronism bit, the difference between the data rate and the write clock frequency due to jitter causes the relative phase of the write clock signal to shift from the data bit to be detected primarily to the adjacent bit midway in the data train (for example, at the portion shown by X in FIG. 7). Thus an error in reading results.
As means for eliminating this error, it could be considered to employ an asynchronous (also referred to as the "start-stop synchronism") communications system using a start and a stop bits. FIG. 8 shows one such example in which the synchronism bits are included because they are needed to distinguish between the data and a possible dropout of the record signal during reproduction and to indicate that data will begin next. Each unit data portion is composed of a frame including one start bit, 8 serial data bits and one stop bit arranged in this order (10 bits in all). Since such form of data train causes the start bit to reset the write clock, the error in reading due to jitter is reduced. That is, as shown in FIG. 8, each time an 8-bit data is read, the write clock is reset and synchronized by the next start bit so that each of the write clock pulses is substantially stably settled at substantially the center of a respective one of the data bits.
While this method alleviates the influence of jitter, it increases redundancy; for example, 10 bytes (80 bits) are needed to record 8-byte data (64 bits). That is, 16 excess code bits are added and the bit utilization measure is reduced.
While the above has been described relative to the problems with the case in which the data signal is recorded and reproduced, together with the audio signal, on and from the magnetic sheet as an example, similar problems will occur with a data signal including especially discrete data signal blocks even in recording and reproduction on and from other recording mediums such as magnetic tape, or in general data transmission and reception.